Semiconductor chip, mounting structure thereof, and methods for forming a semiconductor chip and printed circuit board for the mounting structure thereof

ABSTRACT

A semiconductor chip for flip chip bonding, a mounting structure for the semiconductor chip, and methods for forming a semiconductor chip for flip chip bonding and for fabricating a printed circuit board for a mounting structure of a semiconductor chip are provided which may improve connection between a solder bump of the semiconductor chip and a substrate of the printed circuit board without having to use an underfill material. A polymer core of the solder bump may be supported between a 3-dimensional UBM and a 3-dimensional top surface metallurgy, so as to establish connection strength of the solder bump without using underfill material, and to absorb the stresses which may concentrate on the solder bump due to the difference in coefficients of thermal expansion between metals.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 10/911,705filed on Aug. 5, 2004, now U.S. Pat. No. 7,208,842, and from whichpriority is claimed under 35 U.S.C. §120. This application also claimspriority from Korean Patent Application No. 2003-73863 filed on Oct. 22,2003, in the Korean Intellectual Property Office under 35 U.S.C. §119.The entire contents of both of these applications are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor chip for flip chipbonding, a mounting structure of the semiconductor chip, and methods forforming the semiconductor chip and printed circuit board for mountingstructure of the semiconductor chip.

2. Description of the Related Art

With the development of the semiconductor industry and the pressingdemand of users for high integration density and high speed,semiconductor devices are moving in the direction of an increasingnumber of input/output pins with miniaturization of size. The resultingsemiconductor packages range from insert mount type to surface mounttype and may be configured as ball grid array packages and chip scalepackages, for example.

Wire bonding techniques for interconnection of components onsemiconductor devices include tape automated bonding (TAB) and flip chipbonding techniques. The flip chip bonding technique is generallysuperior to other interconnection techniques in terms of speed,integration density and miniaturization. The flip chip bonding techniquehas been employed in the manufacture of semiconductor chip packages.

FIG. 1 is a partial cross-sectional view of a conventional semiconductorchip for flip chip bonding. Referring to FIG. 1, a semiconductor chip100 used in flip chip bonding typically has a bump of conductivematerial, such as a ball type solder bump 110, for example. Asemiconductor substrate 101 includes an electrode pad 102 of Al or Cufor external electrical connection. A passivation layer 103 is formed onthe substrate 101 such that a portion of the electrode pad 102 isexposed. The solder bump 110 is formed on the exposed electrode pad 102and is connected to the electrode pad 102. A multi-layered under barriermetallurgy (UBM) 109 is formed between the solder bump 110 and theelectrode pad 102.

The UBM 109 includes a barrier metal layer 107 formed on the exposedelectrode pad 102 and a solder wetting layer 108 formed on the barriermetal layer 107. The barrier metal layer 107 may prevent solder materialof the solder bump 110 from permeating into the electrode pad 102 and/orthe semiconductor substrate 101. The solder wetting layer 108 may assistconnection of the solder bump 110.

FIG. 2 is a partial cross-sectional view of the conventionalsemiconductor chip for flip chip bonding, as mounted on a printedcircuit board. Referring to FIG. 2, a substrate 131 of a printed circuitboard (PCB) 130 has a substrate contact pad 132. The solder bump 110 iselectrically and physically connected to the substrate contact pad 132.An underfill resin (not shown) fills an area between the semiconductorchip 100 and the PCB 130 to protect the connected portion from theexternal environment, thereby improving the reliability of theinterconnection.

The conventional semiconductor chip for flip chip bonding of FIG. 1 andmounting structure of FIG. 2 makes it difficult to achieve adequate chipminiaturization. For example, chip miniaturization requires reduced bumpsize and thus a reduced distance between the semiconductor chip 100 andPCB 130. However, the conventional art cannot efficiently perform anunderfill process to fill the area between the semiconductor chip 100and the PCB 130 due to the particle size of the underfill material.

In order to solve the problem, an underfill material having a reducedsize than what is conventionally used is desired. Practically, however,the development of such an underfill material may result in a rise incost. Further, the reduced bump size may result in a reduced area ofconnected portion(s), potentially reducing connection reliability.

SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention is directed to asemiconductor chip for flip chip bonding. The chip may include asemiconductor substrate having integrated circuits; an electrode padformed on the semiconductor substrate and connected to the integratedcircuits, and a passivation layer formed on the semiconductor substrateso that at least a portion of the electrode pad is exposed. A firstunder barrier metallurgy (UBM) layer may be formed on the exposedportion of the electrode pad and passivation layer and connected to theelectrode pad, and a second UBM layer may be formed on the first UBMlayer. A solder layer may be formed on the first UBM layer so as tosubstantially cover the second UBM layer, and a solder bump may beformed on the solder layer and supported by the second UBM layer.

Another exemplary embodiment of the present invention is directed to amounting structure of a semiconductor chip that includes a semiconductorchip as described above and a printed circuit board. The printed circuitboard may include a substrate, contact pad formed on the substrate, anda supporting layer formed on the contact pad. The supporting layer maybe formed so as to be substantially aligned across from the second UBMlayer, so that the supporting layer and second UBM layer support thesolder bump therebetween.

Another exemplary embodiment of the present invention is directed to amethod of forming a semiconductor chip for flip chip bonding. In themethod, an electrode pad may be formed on a semiconductor substrate, anda passivation layer may be formed on the semiconductor substrate so thatat least a portion of the electrode pad is exposed. A first underbarrier metallurgy (UBM) layer may be formed on the exposed portion ofthe electrode pad and passivation layer, and a second UBM layer may beformed on the first UBM layer. A solder layer may be formed on the firstUBM layer so as to substantially cover the second UBM layer, and asolder bump may be formed on the solder layer.

Another exemplary embodiment of the present invention is directed to amethod of fabricating a printed circuit board for a mounting structureof a semiconductor chip. In the method, a contact pad may be formed on asubstrate, and a resin layer may be formed on the semiconductorsubstrate so that at least a portion of the contact pad is exposed toform an opening. A metallurgy layer (UBM) may be formed in the opening,and the resin layer may be removed so as to form the metallurgy layerinto a 3-dimensional shape.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the exemplary embodiments ofthe present invention will be readily understood with reference to thefollowing detailed description thereof provided in conjunction with theaccompanying drawings, wherein like reference numerals designate likestructural elements, and in which:

FIG. 1 is a partial cross-sectional view of a conventional semiconductorchip for flip chip bonding.

FIG. 2 is a partial cross-sectional view of the conventionalsemiconductor chip for flip chip bonding mounted on a printed circuitboard.

FIG. 3 a is a partial cross-sectional view of a semiconductor chip forflip chip bonding in accordance with an exemplary embodiment of thepresent invention.

FIG. 3 b is a cross-sectional view taken along the line I-I′ of FIG. 3a.

FIG. 4 is a partial cross-sectional view of a mounting structure of thesemiconductor chip for flip chip bonding in accordance with an exemplaryembodiment of the present invention.

FIG. 5 is a view showing the simulation results of stresses applied tothe chip to compare the exemplary embodiments of the present inventionto the conventional art.

FIGS. 6 a through 6 f are partial cross-sectional views of a method formanufacturing the semiconductor chip for flip chip bonding in accordancewith an exemplary embodiment of the present invention.

FIGS. 7 a through 7 d are partial cross-sectional views of a method formanufacturing a printed circuit board suitable for the mountingstructure of the semiconductor chip for flip chip bonding.

FIG. 8 is a partial cross-sectional view of a mounting structure of thesemiconductor chip for flip chip bonding in accordance with anotherexemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. The exemplary embodiments of the inventionmay, however, be embodied in different forms and should not be construedas limited to the exemplary embodiments set forth herein. Rather, theseexemplary embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventionto those skilled in the art. In the drawings, the thickness of layersand regions are exaggerated for clarity. It should be understood thatwhen a layer is referred to as being “on” another layer or substrate, itcan be directly on the other layer or substrate, or intervening layersmay also be present. Like numbers refer to like elements throughout.

FIG. 3 a is a partial cross-sectional view of a semiconductor chip forflip chip bonding in accordance with an exemplary embodiment of thepresent invention, and FIG. 3 b is a cross-sectional view taken alongthe line I-I′ of FIG. 3 a.

Referring to FIGS. 3 a and 3 b, a semiconductor chip 300 for flip chipbonding may include a semiconductor substrate 301 having one or moreintegrated circuits. An electrode pad 302 may be formed on thesemiconductor substrate 301 for external electrical connection. Apassivation layer 303 may be formed on the semiconductor substrate 301,so that at least a portion of the electrode pad 302 is left exposed. Afirst under barrier metallurgy (UBM) layer 304 may be formed so as tosubstantially cover the exposed electrode pad 302 and the passivationlayer 303. A 3-dimensional UBM layer 307 may be formed on the first UBM304. A solder layer 308 may be formed on the first UBM 304 so as tosubstantially cover the 3-dimensional UBM 307. A solder bump 310 may beformed on the solder layer 308. The solder bump 310 may include apolymer core 311

The electrode pad 302 may serve as an input/output terminal and becomposed of a metal such as Al or Cu, for example. The passivation layer303 may be embodied as a silicon nitride film, a silicon oxide film or apolyimide, for example. A protection layer (not shown) may optionally beformed on the passivation layer 303.

The first UBM 304 layer may include materials such as Cr, Ti, Ni or TiW,alloys of these materials or combinations of these materials. The firstUBM 304 layer may prevent solder material of the solder bump 310 frompermeating into the electrode pad 302 and/or the semiconductor substrate301.

The 3-dimensional UBM layer 307 may include Ni, Cu, Pd, Pt or an alloythereof. The 3-dimensional UBM layer 307 may support the polymer core311. The 3-dimensional UBM layer 307 may be formed in a shape of a ringhaving a given height. The formation of the 3-dimensional UBM layer 307depends on the desired solder bump 310 to be formed. In other words, the3-dimensional UBM 307 may be formed to a desired size and height so thatthe polymer core 311 of the solder bump 310 “fits” into a cavity orrecess that is formed due to the shape and height of the 3-dimensionalUBM layer 307, as shown in FIGS. 3 a and 3 b, for example.

The solder layer 308 may be composed of one or more of Sn, Pb, Ni, Au,Ag, Cu, Bi or an alloy thereof. The solder layer 308 may assistconnection of the solder bump 310 by providing solder for the solderbump 310, which contains a relatively small amount of solder.

The solder bump 310 may be configured as a ball bump, for example, andincludes the polymer core 311, an adhesive layer 312 surrounding thepolymer core 311 (composed of a material having adequate adhesionproperties such as nickel for example), and a bump solder layer 313surrounding the adhesive layer 312. The adhesive layer 312 may be formedby a non-electrolytic plating method. Commercially, the diameter of thepolymer core 311 may be about 100 μm, the thickness of the adhesivelayer 312 may be about 3 μm and the thickness of the solder layer may beabout 7 μm, although these are only exemplary dimensions. The diameterof the polymer core 311 and the thicknesses of the adhesive layer 312and the bump solder layer 313 may vary based on a desired chip size orapplication.

FIG. 4 is a partial cross-sectional view of a mounting structure of thesemiconductor chip for flip chip bonding in accordance with an exemplaryembodiment of the present invention. The semiconductor chip 300 for flipchip bonding may be directly mounted on a PCB 330, as shown in FIG. 4.The PCB 330 may include a 3-dimensional top surface metallurgy layer 335formed on a contact pad 332, which in turn is formed on a substrate 331.The 3-dimensional top surface metallurgy layer 335 may be formed in theshape of a ring having a given height, and may be located on contact pad332 so as to correspond to the 3-dimensional UBM layer 307. In otherwords, the 3-dimensional top surface metallurgy layer 335 is formed soas to be a ‘mirror image’ of the 3-dimensional UBM layer 307 in terms ofthe spacing between raised portions of the layer 335. Thus, as shown inFIG. 4, the top surface metallurgy layer 335 is formed so as to besubstantially aligned across from the 3-dimensional UBM layer 307 sothat the top surface metallurgy layer 335 and 3-dimensional UBM layer307 support the solder bump 310 therebetween.

As the semiconductor chip 300 is flip-chip bonded to the PCB 330, thesolder bump 310 fits between the 3-dimensional UBM layer 307 and the topsurface metallurgy 335. The polymer core 311 is supported at one end bythe 3-dimensional UBM layer 307 and at the other end by the top surfacemetallurgy layer 335. The stresses may be absorbed by the polymer core311 as a primary absorption structure, and then by the 3-dimensional UBMlayer 307 and/or the 3-dimensional top surface metallurgy layer 335 assecondary absorption structures.

As described above, the semiconductor chip 300 may be configured so thatthe polymer core 311 fits into the 3-dimensional UBM layer 307, Such aconfiguration may provide a structure that can absorb the stresses whichmay be applied to the solder bump 310. The stresses may be absorbedfirst by the polymer core 311 as a primary absorption structure, andthen by the 3-dimensional UBM layer 307 and/or the 3-dimensional topsurface metallurgy 335 layer, each serving as a secondary absorptionstructure.

FIG. 5 is a view showing the simulation results of stresses applied tothe chip to compare the exemplary embodiments of the present inventionto the conventional art. The absorption effect may be illustrated by thefollowing simulation results. Referring to FIG. 5, the stress applied tothe conventional bump shown in the picture on the right-hand side ofFIG. 5 is 23.6 kgf/mm², while the stress applied to the polymer core 311in accordance with the exemplary embodiments of the present invention is14.8 kgf/mm². Although this exemplary embodiment shows a 3-dimensionalUBM layer 307 formed in the shape of a ring, this is only an exemplaryshape; the UBM may be configured in various shapes so as to attainsimilar absorption effects.

FIGS. 6 a through 6 f are partial cross-sectional views of a method formanufacturing the semiconductor chip for flip chip bonding in accordancewith an exemplary embodiment of the present invention. In particular,the views show the progression of steps in forming a semiconductor chipsuch as semiconductor chip 300 of FIGS. 3 a and 3 b.

Referring to FIG. 6 a, a semiconductor substrate 301 is provided. Aplurality of electrode pads 302 are formed on the semiconductorsubstrate 301. A passivation layer 303 is formed such that at least aportion of the electrode pad 302 is exposed. As discussed above, theelectrode pad 302 is made of metals such as Al or Cu.

Referring to FIG. 6 b, a first under barrier metallurgy (UBM) layer 304may be formed so as to substantially cover the passivation layer 303 andthe exposed electrode pad 302. The first UBM layer 304 may be formed bya sputtering method, for example, although.

Referring to FIG. 6 c, a photoresist layer 305 may be formed on thefirst UBM layer 304. The height of the photoresist layer 305 may bedetermined based on a desired size and/or shape of a solder bump to beformed, for example.

Referring to FIG. 6 d, an opening 306 may be created in the photoresistlayer 305 via known exposing and developing processes. The opening 306is formed in the photoresist layer 305 adjacent to the electrode pad 302and exposes a portion of the first UBM layer 304. The opening 306 may beformed in the shape of a ring, although the position and shape of theopenings may vary based on a desired final chip size or structure.

Referring to FIG. 6 e, a 3-dimensional UBM layer 307 may be formed inthe opening 306. The 3-dimensional UBM 307 may be formed using anelectroplating process, for example, so as to have a ring-like shapehaving a given height, as shown in FIG. 3 b.

Referring to FIG. 6 f, after removal of a given portion of thephotoresist layer 305 adjacent to the electrode pad 302 to exposeportions of the first UBM layer 304 and second, 3-dimensional UBM layer307, a solder layer 308 may be formed on the exposed portions. Thesolder layer 308 may be formed to protect against chemical permeationinto the electrode pads 302 and/or the 3-dimensional UBM layer 307, andto supplement the solder bump 310 with further solder. The solder layer308 may be formed by known developing and plating processes, forexample.

Next, the remaining photoresist layer 305 and portions of the first UBMlayer 304 that are beneath the photoresist layer 305 (and not covered bythe solder layer 308) are removed. A conventional etching process may beused to remove exposed portions of the first UBM layer 304 not coveredby the solder layer 308. A solder bump 310 having a polymer core 311 maythen be attached to complete the fabrication process. The solder bump310 may be attached to the 3-dimensional UBM layer 307 using a knownbump attaching apparatus, and may be subjected to a reflow process usinga laser source.

FIGS. 7 a through 7 d are partial cross-sectional views of a method formanufacturing a printed circuit board suitable for a mounting structureof a semiconductor chip for flip chip bonding. Referring to FIG. 7 a,circuit patterns (not shown) and a contact pad 332 are formed on asubstrate 331. A resin layer 333 may be formed so as to substantiallycover the contact pad 332, as shown in FIG. 7 a. Referring to FIG. 7 b,an opening 334 may be formed through resin layer 333 to expose a portionof the contact pad 332. Referring to FIG. 7 c, a top surface metallurgylayer 335 may be formed by filling the opening 334 with a metalmaterial. After the resin layer 333 is removed by a suitable etchingprocess, for example, the printed circuit board 330 has a 3-dimensionaltop surface metallurgy layer 335, as shown in FIG. 7 d. Similar to the3-dimensional UBM layer 307, the 3-dimensional top surface metallurgylayer 335 may be in a ring-like shape at a desired, given height.

FIG. 8 is a partial cross-sectional view of a mounting structure of asemiconductor chip for flip chip bonding in accordance with anotherexemplary embodiment of the present invention. FIG. 8 is somewhatsimilar to FIG. 4, thus the layers and/or structural components havesubstantially the same element numerals as FIG. 4, except that a PCB 350may include a photoresist layer 353 formed on a portion of substrate 351and on a portion of a contact pad 352. Thus, instead of forming a3-dimensional top surface metallurgy layer 335 to support solder bump310, the photoresist layer 353 is formed to support the polymer core 311of the solder bump 310, thereby improving the reliability of the flipchip bonding.

In accordance with of the exemplary embodiments of the presentinvention, a mounting structure of a semiconductor chip may include asolder bump having a core, a 3-dimensional UBM layer and a 3-dimensionaltop surface metallurgy layer to provide sufficient connection strengthfor the solder bump without using underfill material, and may absorb thestresses which may concentrate on the solder bump due to differences inthe coefficients of thermal expansion of various metals of the layersand/or components of the mounting structure.

Although the exemplary embodiments of the present invention have beendescribed in detail hereinabove, it should be understood that manyvariations and/or modifications of the basic inventive concepts hereintaught, which may appear to those skilled in the art, will still fallwithin the spirit and scope of the exemplary embodiments of the presentinvention as defined in the appended claims.

1. A method of forming a semiconductor chip for flip chip bonding,comprising: forming an electrode pad on a semiconductor substrate;forming a passivation layer on the semiconductor substrate so that atleast a portion of the electrode pad is exposed; forming a first underbarrier metallurgy (UBM) layer on the exposed portion of the electrodepad and passivation layer; forming a second UBM layer on the first UBMlayer; forming a solder layer directly on the first UBM layer so as tosubstantially cover the second UBM layer; and forming a solder bump onthe solder layer.
 2. The method of claim 1, wherein forming a second UBMlayer comprises forming a 3-dimensional UBM.
 3. The method of claim 2,wherein the solder bump includes a polymer core, and the 3-dimensionalUBM supports the solder bump so that the polymer core fits into the UBM.4. The method of claim 2, wherein the 3-dimensional UBM is formed in theshape of a ring.
 5. A semiconductor chip for flip chip bonding, the chipincluding a substrate, an electrode pad on the substrate, a passivationlayer on the semiconductor substrate so that a portion of the electrodepad is exposed, a first under barrier metallurgy (UBM) on the exposedportion of the electrode pad and passivation layer and connected to theelectrode pad, a second UBM layer on the first UBM layer, a solder layeron the first UBM layer so as to substantially cover the second UBMlayer, and a solder bump on the solder layer and supported by the secondUBM layer, the chip formed by the method of claim
 1. 6. A mountingstructure of a semiconductor chip, comprising a semiconductor chip and aprinted circuit board, the printed circuit board including a metallurgylayer on a contact pad, the contact pad provided on a substrate, theprinted circuit board fabricated by the method of claim 5.